As semiconductor devices become more highly integrated and are required to operate at higher speeds, it may be desirable to form finer patterns in a semiconductor substrate and to reduce the spacing between patterns in a semiconductor substrate. Accordingly, a great deal of emphasis has been placed on developing the technology for filling up the intervals between patterns on a semiconductor substrate with isolation structures that have reduced defects such as voids and/or seams.
Examples of structures in semiconductor devices which may be used to fill the space between patterns include a trench device isolation layer, a sacrificial layer for separating nodes of a lower electrode of a cylindrical capacitor, an insulation interlayer between gate patterns, etc. Some of these structures such as the trench device isolation layer, the sacrificial layer or the insulation interlayer may include a silicon oxide formed using a chemical vapor deposition (CVD) process.
However, CVD-deposited silicon oxide may have the problem of poor step coverage. That is, when a recess having an aspect ratio (i.e., ratio of height to width) of, for example, over about three, is filled with CVD-deposited silicon oxide, an overhang may be generated at an upper portion of the recess. Layer defects such as voids and/or seams may be created in the silicon oxide layer due to such an overhang.